FPGA
CARTRIDGE FOR MSX Purpose:
Just a quick html page to explain how i connected an fpga to an msx
cartridge slot and run first trial test .
Chronology
1)
I have been reading the following link about an extension
catridge for prototyping with apple IIe
and commodore on msx.org :
http://www.msx.org/forumtopic5434p15.html
I bought it but noticed then realized than shape factor was not fitting
in an msx easily ( at least
Tr series ) I also noticed a location for soldering a plcc altera fpga
: i then started thinking
to add an fpga to msx to build an extension .
2)
Since i am staying in france and i am more a xilinx guy i used the
following links to make
the pcb and get the fpga module :
http://www.circuit-electronique.fr/PBCPPlayer.asp?ID=119136
---> it is a good site , they even provide the cad software for
pcb drawing )
http://www.enterpoint.co.uk/component_replacements/craignell.html
---> i got a pair of module in dil40 format with
spartan 3E 100 devices ( expensive )
3)
soldered a zif 40 on the pcb, wires with a 8kb SRAM/EEPROM scheme ,
actually
tested it in first place with a 8kb sram and 8kb eeprom, stiched my
jtag usb cable i
got here
.
4) here we are for the hardware !
front side
VHDL code for
trial :
I compiled this with xilinx ise 10.1 :
entity msxext is
Port ( clk : in std_logic;
data : inout STD_LOGIC_VECTOR (7 downto 0);
addr : in STD_LOGIC_VECTOR (7 downto 0);
iorq : in STD_LOGIC;
rd : in STD_LOGIC;
wr : in STD_LOGIC;
led : out std_logic);
end msxext;
architecture Behavioral of msxext is
signal regs88,regs89 : std_logic_vector(7 downto 0);
begin
rom : process(clk)
begin
if (clk='1' and clk'event)
then
if (rd ='0' and iorq ='0' and
addr="10001000") then
data <= "10101011";
else
data <= (others => 'Z'
);
end if;
end if;
end process;
led <= iorq;
end Behavioral;
And the ucf constraint file was stripped down from enterpoint
site :
NET "CLK" TNM_NET = "CLK";
TIMESPEC "TS_CLK" = PERIOD "CLK" 25 ns HIGH 50 %;
OFFSET = IN 5 ns BEFORE "CLK" ;
OFFSET = OUT 15 ns AFTER "CLK" ;
NET
"clk"
LOC = "M6" | IOSTANDARD = LVTTL;
NET
"led"
LOC = "C14" | IOSTANDARD = LVTTL;
NET
"addr(7)"
LOC="F3" | IOSTANDARD = LVTTL ;
#IO2
NET
"addr(6)"
LOC="A3" | IOSTANDARD = LVTTL ;
#IO3
NET
"addr(5)"
LOC="H3" | IOSTANDARD = LVTTL ;
#IO35
NET
"addr(4)"
LOC="J3" | IOSTANDARD = LVTTL ;
#IO36
NET
"addr(3)"
LOC="H1" | IOSTANDARD = LVTTL ;
#IO37
NET
"addr(2)"
LOC="F1" | IOSTANDARD = LVTTL ;
#IO34
NET
"addr(1)"
LOC="M4" | IOSTANDARD = LVTTL ;
#IO38
NET
"addr(0)"
LOC="L3" | IOSTANDARD = LVTTL ;
#IO26
NET
"data(0)"
LOC="P4" | IOSTANDARD = LVTTL ;
#IO33
NET
"data(1)"
LOC="M5" | IOSTANDARD = LVTTL ;
#IO32
NET
"data(2)"
LOC="P6" | IOSTANDARD = LVTTL ;
#IO31
NET
"data(3)"
LOC="P7" | IOSTANDARD = LVTTL ;
#IO30
NET
"data(4)"
LOC="M12" | IOSTANDARD = LVTTL ;
#IO28
NET
"data(5)"
LOC="L14" | IOSTANDARD = LVTTL ;
#IO27
NET
"data(6)"
LOC="N14" | IOSTANDARD = LVTTL ;
#IO25
NET
"data(7)"
LOC="H12" | IOSTANDARD = LVTTL ;
#IO24
NET "rd"
LOC="J14" | IOSTANDARD = LVTTL ;
#IO21
And finally powered on MSX and downloaded bitfile :
And fillany run the test ( the vhdl code behaves like a status port on
address &h88 ) :
