msx3D Project Status (06/30/2009 - 22:19:31)
Project File:	msx3D.ise	Current State:	Placed and Routed
Module Name:	msx3d	Errors:	No Errors
Target Device:	xc3s100e-4cp132	Warnings:	24 Warnings
Product Version:	ISE 10.1 - WebPACK	Routing Results:	All Signals Completely Routed
Design Goal:	Balanced	Timing Constraints:	All Constraints Met
Design Strategy:	Xilinx Default (unlocked)	Final Timing Score:	0 (Timing Report)

 

msx3D Partition Summary				[-]
No partition information was found.

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Number of Slice Flip Flops	217	1,920	11%
Number of 4 input LUTs	1,069	1,920	55%
Logic Distribution
Number of occupied Slices	611	960	63%
Number of Slices containing only related logic	611	611	100%
Number of Slices containing unrelated logic	0	611	0%
Total Number of 4 input LUTs	1,081	1,920	56%
Number used as logic	1,069
Number used as a route-thru	12
Number of bonded IOBs	65	83	78%
Number of RAMB16s	4	4	100%
Number of BUFGMUXs	1	24	4%
Number of MULT18X18SIOs	2	4	50%

 

Performance Summary				[-]
Final Timing Score:	0	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	mar. 30. juin 22:17:04 2009	0	10 Warnings	6 Infos
Translation Report	Current	mar. 30. juin 22:17:18 2009	0	0	0
Map Report	Current	mar. 30. juin 22:18:42 2009	0	14 Warnings	12 Infos
Place and Route Report	Current	mar. 30. juin 22:19:19 2009	0	0	0
Static Timing Report	Current	mar. 30. juin 22:19:30 2009	0	0	2 Infos
Bitgen Report	Out of Date	lun. 22. juin 12:31:39 2009	0	0	0

Date Generated: 06/30/2009 - 22:19:31